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Features
* Incorporates the ARM7TDMI (R) ARM(R) Thumb(R) Processor
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt EmbeddedICETM In-circuit Emulation, Debug Communication Channel Support 256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes - Single Cycle Access at Up to 30 MHz in Worst Case Conditions - Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed - Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms - 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities 32K Bytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed Memory Controller (MC) - Embedded Flash Controller, Abort Status and Misalignment Detection - Memory Protection Unit Reset Controller (RSTC) - Based on Three Power-on Reset Cells - Provides External Reset Signal Shaping and Reset Sources Status Clock Generator (CKGR) - Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL Power Management Controller (PMC) - Power Optimization Capabilities, including Slow Clock Mode (Down to 500 Hz), Idle Mode, Standby Mode and Backup Mode - Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Four External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel interrupt Periodic Interval Timer (PIT) - 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) - 12-bit key-protected Programmable Counter - Provides Reset or Interrupt Signal to the System - Counter May Be Stopped While the Processor is in Debug Mode or in Idle State Real-time Timer (RTT) - 32-bit Free-running Counter with Alarm - Runs Off the Internal RC Oscillator Two Parallel Input/Output Controllers (PIO) - Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up resistor and Synchronous Output Shutdown Controller (SHDWC) - Programmable Shutdown Pin and Wake-up Circuitry Two 32-bit Battery Backup Registers for a Total of 8 Bytes One 8-channel 20-bit PWM Controller (PWMC) One USB 2.0 Full Speed (12 Mbits per Second) Device Port - On-chip Transceiver, 2376-byte Configurable Integrated FIFOs
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Product Description AT91SAM7A3 Preliminary Summary
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NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com.
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* Nineteen Peripheral DMA Controller (PDC) Channels * Two CAN 2.0B Active Controllers, Supporting 11-bit Standard and 29-bit Extended Identifiers * *
- 16 Fully Programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two 8-channel 10-bit Analog-to-Digital Converter Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA(R) Infrared Modulation/Demodulation - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interfaces (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three 3-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two Synchronous Serial Controllers (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One Two-wire Interface (TWI) - Master Mode Support Only, All Two-wire Atmel EEPROM's Supported Multimedia Card Interface (MCI) - Compliant with Multimedia Cards and SD Cards - Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant IEEE(R) 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies - Embedded 1.8V Regulator, Drawing up to 130 mA for the Core and the External Components, Enables 3.3V Single Supply Mode - 3.3V VDD3V3 Regulator, I/O Lines and Flash Power Supply - 1.8V VDD1V8 Output of the Voltage Regulator and Core Power Supply - 3V to 3.6V VDDANA ADC Power Supply - 3V to 3.6V VDDBU Backup Power Supply 5V-tolerant I/Os Fully Static Operation: Up to 60 MHz at 1.65V and 85C Worst Case Conditions Available in a 100-lead LQFP Green Package
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1. Description
The AT91SAM7A3 is a member of a series of 32-bit ARM7TM microcontrollers with an integrated CAN controller. It features a 256-Kbyte high-speed Flash and 32-Kbyte SRAM, a large set of peripherals, including two 2.0B full CAN controllers, and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface. Builtin lock bits protect the firmware from accidental overwrite. The AT91SAM7A3 integrates a complete set of features facilitating debug, including a JTAG Embedded ICE interface, misalignment detector, interrupt driven debug communication channel for user configurable trace on a console, and JTAG boundary scan for board level debug and test. By combining a high-performance 32-bit RISC processor with a high-density 16-bit instruction set, Flash and SRAM memory, a wide range of peripherals including CAN controllers, 10-bit ADC, Timers and serial communication channels, on a monolithic chip, the AT91SAM7A3 is ideal for many compute-intensive embedded control applications.
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2. Block Diagram
Figure 2-1. AT91SAM7A3 Block Diagram
TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0-IRQ3 DRXD DTXD PCK0-PCK3 PLLRC XIN XOUT GND VDDBU FWKUP WKUP0 WKUP1 SHDW VDDBU VDD3V3
PIO
JTAG SCAN System Controller AIC
PDC
ICE
ARM7TDMI Processor
1.8 V Voltage Regulator
VDD3V3 GND VDD1V8
DBGU
PDC
FLASH 256K Bytes Memory Controller SRAM 32K Bytes
Embedded Flash Controller Memory Protection Unit Address Decoder Abort Status Misalignment Detection
PLL OSC
GPBR
PMC
RCOSC
RTT Shutdown Controller
Peripheral Bridge Peripheral Data Controller 19 channels
POR POR
VDD1V8 POR
APB
FIFO
Transceiver
Reset Controller
USB Device PIT
TWI
DDM DDP
NRST
WDT PIOA
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK MCCK MCCDA MCDA0-MCDA3 ADC0_AD0 ADC0_AD1 ADC0_AD2 ADC0_AD3 ADC0_AD4 ADC0_AD5 ADC0_AD6 ADC0_AD7 ADC0_ADTRG ADVREFP VDDANA GND ADC1_AD0 ADC1_AD1 ADC1_AD2 ADC1_AD3 ADC1_AD4 ADC1_AD5 ADC1_AD6 ADC1_AD7 ADC1_ADTRG
CAN0 CAN1
PDC
PIOB
USART0
PDC PDC
PWMC
USART1
PDC PDC
PDC
USART2
PDC PDC
PDC PDC
SSC1
PDC
SPI0
PDC PDC
PIO
SSC0
TWD TWCK CANRX0 CANTX0 CANRX1 CANTX1 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TCLK3 TCLK4 TCLK5 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 TCLK6 TCLK7 TCLK8 TIOA6 TIOB6 TIOA7 TIOB7 TIOA8 TIOB8
Timer Counter TC0 TC1
PDC PDC
SPI1
PIO
TC2 Timer Counter TC3 TC4 TC5
MCI
PDC
ADC0
PDC
Timer Counter TC6
ADC1
TC7 TC8
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3. Signal Description
Table 3-1.
Signal Name
Signal Description
Function Power Type Active Level Comments
VDD3V3 VDDBU VDDANA VDD1V8 VDDPLL GND
1.8V Voltage Regulator, I/O Lines and Flash Power Supply Backup I/O Lines Power Supply Analog Power Supply 1.8V Voltage Regulator Output and Core Power Supply 1.8V PLL Power Supply Ground
Power Power Power Power Power Ground
3.0V to 3.6V 3V to 3.6V 3V to 3.6V 1.85V typical 1.65V to 1.95V
Clocks, Oscillators and PLLs XIN XOUT PLLRC PCK0 - PCK3 SHDW WKUP0 - WKUP1 FWKUP Main Oscillator Input Main Oscillator Output PLL Filter Programmable Clock Output Shut-Down Control Wake-Up Inputs Force Wake Up ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Reset/Test NRST TST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data Input Output I/O Input Low High Pull-down resistor Input Input Output Input Input No pull-up resistor Pull-down resistor No pull-up resistor No pull-up resistor Input Output Input Output Output Input Input Open Drain. Accept between 0V and VDDBU Accept between 0V and VDDBU External pull-up resistor needed.
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Table 3-1.
Signal Name
Signal Description (Continued)
Function AIC Type Active Level Comments
IRQ0 - IRQ3 FIQ
External Interrupt Inputs Fast Interrupt Input PIO
Input Input
PA0 - PA31 PB0 - PB29
Parallel IO Controller A Parallel IO Controller B
I/O I/O
Pulled-up input at reset Pulled-up input at reset
Multimedia Card Interface MCCK MCCDA MCDA0 - MCDA3 Multimedia Card Clock Multimedia Card A Command Multimedia Card A Data USB Device Port DDM DDP USB Device Port Data USB Device Port Data + USART SCK0 - SCK1 - SCK2 TXD0 - TXD1 - TXD2 RXD0 - RXD1 - RXD2 RTS0 - RTS1 - RTS2 CTS0 - CTS1 - CTS2 Serial Clock Transmit Data Receive Data Request To Send Clear To Send I/O I/O Input Output Input Synchronous Serial Controller TD0 - TD1 RD0 - RD1 TK0 - TK1 RK0 - RK1 TF0 - TF1 RF0 - RF1 Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Timer/Counter TCLK0 - TCLK8 TIOA0 - TIOA8 TIOB0 - TIOB8 External Clock Input I/O Line A I/O Line B PWM Controller PWM0 - PWM7 PWM Channels Output Input I/O I/O Output Input I/O I/O I/O I/O Analog Analog Output I/O I/O
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Table 3-1.
Signal Name
Signal Description (Continued)
Function SPI Type Active Level Comments
SPI0_MISO SPI1_MISO SPI0_MOSI SPI1_MOSI SPI0_SPCK SPI1_SPCK SPI0_NPCS0 SPI1_NPCS0 SPI0_NPCS1 - SPI0_NPCS3 SPI1_NPCS1 - SPI1_NPCS3
Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select Two-wire Interface
I/O I/O I/O I/O Output Low Low
TWD TWCK
Two-wire Serial Data Two-wire Serial Clock
I/O I/O
Analog-to-Digital Converter ADC0_AD0 - ADC0_AD7 ADC1_AD0 - ADC1_AD7 ADVREFP ADC0_ADTRG ADC1_ADTRG Analog Inputs Analog Positive Reference ADC Trigger CAN Controller CANRX0-CANRX1 CANTX0-CANTX1 CAN Inputs CAN Outputs Input Output Analog Analog Input Digital pulled-up inputs at reset
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4. Package
4.1 100-lead LQFP Package Outline
Figure 4-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-1. 100-lead LQFP Outline (Top View)
75 76 51 50
100 1 25
26
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4.2 Pinout
Pinout in 100-lead LQFP Package
GND NRST TST PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 VDD3V3 GND VDD1V8 PB2 PB1 PB0 PA0 PA1 PA2 PA3 GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDBU FWKUP WKUP0 WKUP1 SHDW GND PA4 PA5 PA6 PA7 PA8 PA9 VDD3V3 GND VDD1V8 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 VDD1V8 GND VDD3V3 PA28 PA29 PA30 PA31 JTAGSEL TDI TMS TCK TDO GND VDDPLL XOUT XIN GND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PLLRC VDDANA ADVREFP GND PB14/ADC0_AD0 PB15/ADC0_AD1 PB16/ADC0_AD2 PB17/ADC0_AD3 PB18/ADC0_AD4 PB19/ADC0_AD5 PB20/ADC0_AD6 PB21/ADC0_AD7 VDD3V3 PB22/ADC1_AD0 PB23/ADC1_AD1 PB24/ADC1_AD2 PB25/ADC1_AD3 PB26/ADC1_AD4 PB27/ADC1_AD5 PB28/ADC1_AD6 PB29/ADC1_AD7 DDM DDP VDD1V8 VDD3V3
Table 4-1.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
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5. Power Considerations
5.1 Power Supplies
The AT91SAM7A3 has five types of power supply pins: * VDD3V3 pins. They power the voltage regulator, the I/O lines, the Flash and the USB transceivers; voltage ranges from 3.0V to 3.6V, 3.3V nominal. * VDD1V8 pins. They are the outputs of the 1.8V voltage regulator and they power the logic of the device. * VDDPLL pin. It powers the PLL; voltage ranges from 1.65V to 1.95V, 1.8V typical. They can be connected to the VDD1V8 pin with decoupling capacitor. * VDDBU pin. It powers the Slow Clock oscillator and the Real Time Clock, as well as a part of the System Controller; ranges from 3.0V and 3.6V, 3.3V nominal. * VDDANA pin. It powers the ADC; ranges from 3.0V and 3.6V, 3.3V nominal. No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.
5.2
Voltage Regulator
The AT91SAM7A3 embeds a voltage regulator that consumes less than 120 A static current and draws up to 130 mA of output current. Adequate output supply decoupling is mandatory for VDD1V8 (pin 99)to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDD1V8 and GND as close to the chip as possible. One external 3.3 F (or 4.7 F) X7R capacitor must be connected between VDD1V8 and GND. All other VDD1V8 pins must be externally connected and have a proper decoupling capacitor (at least 100 nF). Adequate input supply decoupling is mandatory for VDD3V3 (pin 100) in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 F X7R. All other VDD3V3 pins must be externally connected and have a proper decoupling capacitor (at least 100 nF).
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5.3
5.3.1
Typical Powering Schematics
3.3V Single Supply The AT91SAM7A3 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDPLL. Figure 5-1 shows the power schematics to be used for USB bus-powered systems. Figure 5-1. 3.3V System Single Power Supply Schematics
VDDBU DC/DC Converter USB Connector up to 5.5V 3.3V VDD1V8 VDDPLL VDDANA VDD3V3 Voltage Regulator
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6. I/O Lines Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5V-tolerant, TDI is not. TMS, TDI and TCK do not integrate any resistors and have to be pulled-up externally. TDO is an output, driven at up to VDD3V3. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor so that it can be left unconnected for normal operations.
6.2
Test Pin
The TST pin is used for manufacturing tests and integrates a pull-down resistor so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results.
6.3
Reset Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the NRST signal to reset all the components of the system.
6.4
PIO Controller A and B Lines
All the I/O lines PA0 to PA31 and PB0 to PB29 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDD3V3, but can be driven with a voltage at up to 5.5V. However, driving an I/O line with a voltage over VDD3V3 while the programmable pull-up resistor is enabled creates a current path through the pull-up resistor from the I/O line to VDDIO. Care should be taken, especially at reset, as all the I/O lines default as inputs with pull-up resistor enabled at reset.
6.5
Shutdown Logic Pins
The SHDW pin is an open drain output. It can be tied to VDDBU with an external pull-up resistor. The FWUP, WKUP0 and WKUP1 pins are input-only. They can accept voltages only between 0V and VDDBU. It is recommended to tie these pins either to GND or to VDDBU with an external resistor.
6.6
I/O Line Drive Levels
All the I/O lines can draw up to 2 mA.
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7. Processor and Architecture
7.1 ARM7TDMI Processor
* RISC Processor Based on ARMv4T Von Neumann Architecture - Runs at up to 60 MHz, providing 0.9 MIPS/MHz * Two instruction sets - ARM high-performance 32-bit Instruction Set - Thumb high code density 16-bit Instruction Set * Three-stage pipeline architecture - Instruction Fetch (F) - Instruction Decode (D) - Execute (E)
7.2
Debug and Test Features
* Integrated EmbeddedICETM (embedded in-circuit emulator) - Two watchpoint units - Test access port accessible through a JTAG protocol - Debug communication channel * Debug Unit - Two-pin UART - Debug communication channel interrupt handling - Chip ID Register * IEEE1149.1 JTAG Boundary-scan on all digital pins
7.3
Memory Controller
* Bus Arbiter - Handles requests from the ARM7TDMI and the Peripheral Data Controller * Address Decoder Provides Selection Signals for - Three internal 1Mbyte memory areas - One 256 Mbyte embedded peripheral area * Abort Status Registers - Source, Type and all parameters of the access leading to an abort are saved - Facilitates debug by detection of bad pointers * Misalignment Detector - Alignment checking of all data accesses - Abort generation in case of misalignment * Remap Command - Remaps the Internal SRAM in place of the embedded non-volatile memory - Allows handling of dynamic exception vectors * 16-area Memory Protection Unit - Individually programmable size between 1K Bytes and 1M Bytes
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- Individually programmable protection against write and/or user access - Peripheral protection against write and/or user access * Embedded Flash Controller - Embedded Flash interface, up to three programmable wait states - Read-optimized interface, buffering and anticipating the 16-bit requests, reducing the required wait states - Password-protected program, erase and lock/unlock sequencer - Automatic consecutive programming, erasing and locking operations - Interrupt generation in case of forbidden operation
7.4
Peripheral DMA Controller
* Handles data transfer between peripherals and memories * Nineteen Channels - Two for each USART - Two for the Debug Unit - Two for each Serial Synchronous Controller - Two for each Serial Peripheral Interface - One for the Multimedia Card Interface - One for each Analog-to-Digital Converter * Low bus arbitration overhead - One Master Clock cycle needed for a transfer from memory to peripheral - Two Master Clock cycles needed for a transfer from peripheral to memory * Next Pointer management for reducing interrupt latency requirements
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8. Memory
8.1 Embedded Memories
* 256 Kbytes of Flash Memory - 1024 pages of 256 bytes. - Fast access time, 30 MHz single cycle access in worst case conditions. - Page programming time: 6 ms, including page auto-erase - Full erase time: 15 ms - 10,000 write cycles, 10-year data retention capability - 16 lock bits, each protecting 16 pages * 32 Kbytes of Fast SRAM - Single-cycle access at full speed
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Figure 8-1.
AT91SAM7A3 Memory Mapping
Internal Memory Mapping
0x0000 0000
Flash before Remap SRAM after Remap
0x000F FFF 0x0010 0000
1 MBytes
Internal Flash
0x001F FFF 0x0020 0000
1 MBytes
Internal SRAM
0x002F FFF 0x0030 0000
1 MBytes 252 MBytes
Reserved
0x0FFF FFFF
Address Memory Space 0x0000 0000
Internal Memories
256 MBytes
Peripheral Mapping
0x0FFF FFFF 0x1000 0000
0xF000 0000 0xFFF7 FFFF 0xFFF8 0000 0xFFF8 3FFF 0xFFF8 4000 0xFFF8 7FFF 0xFFF8 8000 0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF 0xFFFA 4000 Reserved
System Controller Mapping 0xFFFF F000
CAN0 CAN1 Reserved TC0, TC1, TC2 TC3, TC4, TC5 TC6, TC7, TC8 MCI UDP Reserved
16 Kbytes AIC 16 Kbytes 0xFFFF F1FF 0xFFFF F200 DBGU 0xFFFF F3FF 0xFFFF F400 PIOA 0xFFFF F5FF 0xFFFF F600 PIOB 0xFFFF F7FF 0xFFFF F800 Reserved 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes MC 256 Bytes/64 registers 0xFFFF FBFF 0xFFFF FC00 PMC 256 Bytes/64 registers 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD10 0xFFFF FD1F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD50 0xFFFF FC58 0xFFFF FD59 0xFFFF FEFF 0xFFFF FF00 512 Bytes/128 registers 512 Bytes/128 registers 512 Bytes/128 registers 512 Bytes/128 registers
16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes
Undefined (Abort)
14 x 256 MBytes 3,584 MBytes
0xFFFA 7FFF 0xFFFA 8000 0xFFFA BFFF 0xFFFA C000 0xFFFA FFFF 0xFFFB 0000 0xFFFB 3FFF 0xFFFB 4000 0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000
TWI Reserved USART0 USART1 USART2 PWMC SSC0 SSC1 ADC0 ADC1 SPI0 SPI1 Reserved SYSC
16 Kbytes
0xEFFF FFFF
0xF000 0000
0xFFFB FFFF 0xFFFC 0000 0xFFFC 3FFF 0xFFFC 4000
Internal Peripherals
256 MBytes
0xFFFC 7FFF 0xFFFC 8000 0xFFFC BFFF 0xFFFC C000
RSTC SHDWC RTT PIT WDT GPBR Reserved
16 Bytes/4 registers
0xFFFF FFFF
0xFFFC FFFF 0xFFFD 0000 0xFFFD 3FFF 0xFFFD 4000 0xFFFD 7FFF 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 0xFFFD FFFF 0xFFFE 0000 0xFFFE 3FFF 0xFFFE 4000 0xFFFE 7FFF 0xFFFE 8000 0xFFFF EFFF 0xFFFF F000 0xFFFF FFFF
16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 8 Bytes/2 registers general purpose backup registers
0xFFFF FFFF
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8.2
8.2.1
Memory Mapping
Internal SRAM The AT91SAM7A3 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.
8.2.2
Internal Flash The AT91SAM7A3 features one bank of 256 Kbytes of Flash. The Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command. Figure 8-2. Internal Memory Mapping
0x0000 0000
0x000F FFFF
Flash Before Remap SRAM After Remap Internal Flash
1M Bytes
0x0010 0000 1M Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
1M Bytes
Undefined Areas (Abort)
253M Bytes
0x0FFF FFFF
8.3
8.3.1
Embedded Flash
Flash Overview The Flash block of the AT91SAM7A3 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. The Flash block contains a 256-byte write buffer, accessible through a 32-bit interface. When Flash is not used (read or write access), it is automatically put into standby mode.
8.3.2
Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface mapped within the Memory Controller on the APB. The User Interface allows: * programming of the access parameters of the Flash (number of wait states, timings, etc.) * starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. * getting the end status of the last command * getting error status * programming interrupts on the end of the last commands or on errors 17
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The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. 8.3.3 Lock Regions The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the Flash against inadvertent Flash erasing or programming commands. The AT91SAM7A3 has 16 lock regions. Each lock region contains 16 pages of 256 bytes. Each lock region has a size of 4 Kbytes, thus only the first 64 Kbytes can be locked. The 16 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" activates the protection. The command "Clear Lock Bit" unlocks the lock region.
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9. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4K bytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Each peripheral has an address space of up to 512 Bytes, representing up to 128 registers. Figure 9-1 on page 20 shows the System Controller Block Diagram. Figure 8-1 on page 16 shows the mapping of the User Interface of the System Controller peripherals. Note that the Memory Controller configuration user interface is also mapped within this address space.
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Figure 9-1.
System Controller Block Diagram
System Controller
irq0-irq1-irq2-irq3 fiq periph_irq[2..27] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd wdt_fault WDRPROC jtag_nreset
Boundary Scan TAP Controller
nirq nfiq
Advanced Interrupt Controller
proc_nreset int PCK debug
ARM7TDMI
dbgu_irq
Debug Unit
dbgu_txd
ice_nreset
VDD3V3 POR VDD1V8 POR
NRST
periph_nreset ice_nreset jtag_nreset flash_poe proc_nreset
Reset Controller
proc_nreset rstc_irq
Embedded Flash
VDDBU POR
SLCK
VDD1V8 Powered Real-Time Timer
rtt_irq MCK proc_nreset
SLCK periph_nreset FWKUP WKUP0 WKUP1 SHDW
Memory Controller
Shutdown Controller VDDBU Powered RCOSC
SLCK
4 General-Purpose Backup Regs
XIN XOUT
MAIN OSC
MAINCK periph_clk[2..27] pck[0-3] UDPCK periph_clk[27] periph_nreset periph_irq[27]
PLLRC
PLL
int periph_nreset MCK debug periph_nreset SLCK debug idle proc_nreset periph_nreset periph_clk[2..3] dbgu_rxd
PLLCK
Power Management Controller
PCK UDPCK MCK pmc_irq idle
USB Device Port
Periodic Interval Timer Watchdog Timer
pit_irq periph_clk[4..26] periph_nreset
wdt_irq wdt_fault WDRPROC periph_irq{2..3] irq0-irq1-irq2-irq3
periph_irq[4..26]
Embedded Peripherals
PIOs Controller
fiq dbgu_txd in out enable
PA0-PA31 PB0-PB29
9.1
System Controller Mapping
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9.2 Reset Controller
The Reset Controller is based on three power-on reset cells. It gives the status of the last reset, indicating whether it is a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. In addition, it controls the internal resets and the NRST pin output. It shapes a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.
9.3
Clock Generator
The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: - RC Oscillator ranges between 22 KHz and 42 KHz - Main Oscillator frequency ranges between 3 and 20 MHz - Main Oscillator can be bypassed - PLL output ranges between 80 and 220 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2. Clock Generator Block Diagram
Clock Generator
Embedded RC Oscillator XIN XOUT
Slow Clock SLCK
Main Oscillator
Main Clock MAINCK
PLLRC
PLL and Divider
PLL Clock PLLCK Control
Status
Power Management Controller
9.4
Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide: - the Processor Clock PCK - the Master Clock MCK - the USB Clock UDPCK - all the peripheral clocks, independently controllable - four programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thereby reducing power consumption while waiting an interrupt.
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Figure 9-3.
Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int
periph_clk[2..26]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64
pck[0..3]
USB Clock Controller ON/OFF PLLCK Divider /1,/2,/4
UDPCK
9.5
Advanced Interrupt Controller
* Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor * Individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (ST, PMC, DBGU, etc.) - Other sources control the peripheral interrupts or external interrupts - Programmable edge-triggered or level-sensitive internal sources - Programmable positive/negative edge-triggered or high/low level-sensitive external sources (FIQ, IRQ) * 8-level Priority Controller - Drives the normal interrupt nIRQ of the processor - Handles priority of the interrupt sources - Higher priority interrupts can be served during service of a lower priority interrupt * Vectoring - Optimizes interrupt service routine branch and execution - One 32-bit vector register per interrupt source - Interrupt vector register reads the corresponding current interrupt vector * Protect Mode - Easy debugging by preventing automatic operations * Fast Forcing - Permits redirecting any interrupt source on the fast interrupt * General Interrupt Mask - Provides processor synchronization on events without triggering an interrupt
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9.6 Debug Unit
* Comprises - One two-pin UART - One interface for the Debug Communication Channel (DCC) support - One set of chip ID registers - One interface allowing ICE access prevention * Two-pin UART - USART-compatible user interface - Programmable baud rate generator - Parity, framing and overrun error - Automatic Echo, Local Loopback and Remote Loopback Channel Modes * Debug Communication Channel Support - Offers visibility of COMMRX and COMMTX signals from the ARM Processor * Chip ID Registers - Identification of the device revision, sizes of the embedded memories, set of peripherals - Chip ID is 0x260A0941 (Version 1)
9.7
Period Interval Timer
* 20-bit programmable counter plus 12-bit interval counter
9.8
Watchdog Timer
* 12-bit key-protected Programmable Counter running on prescaled SLCK * Provides reset or interrupt signals to the system * Counter may be stopped while the processor is in debug state or in idle mode
9.9
Real-time Timer
* 32-bit free-running counter with alarm * Programmable 16-bit prescaler for SCLK accuracy compensation
9.10
Shutdown Controller
* Software programmable assertion of the SHDW open-drain pin * De-assertion programmable with the pins WKUP0, WKUP1 and FWKUP
9.11
PIO Controllers A and B
* The PIO Controllers A and B respectively control 32 and 30 programmable I/O Lines * Fully programmable through Set/Clear Registers * Multiplexing of two peripheral functions per I/O Line * For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) - Input change interrupt - Half a clock period Glitch filter - Multi-drive option enables driving in open drain
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- Programmable pull up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time * Synchronous output, provides Set and Clear of several I/O lines in a single write
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10. Peripherals
10.1 Peripheral Mapping
Each User Peripheral is allocated 16K bytes of address space. Figure 10-1. User Peripherals Mapping
Address
0xF000 0000
Peripheral
Peripheral Name
Size
Reserved
0xFFF7 FFFF
0xFFF8 0000
0xFFF8 3FFF
CAN0
CAN Controller 0
16K Bytes
0xFFF8 4000
0xFFF8 7FFF 0xFFF8 8000
CAN1
CAN Controller 1
16K Bytes
Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF
TC0, TC1, TC2
Timer/Counter 0, 1 and 2
16K Bytes
0xFFFA 4000
0xFFFA 7FFF
TC3, TC4, TC5
Timer/Counter 3, 4 and 5
16K Bytes
0xFFFA 8000
0xFFFA BFFF
TC6, TC7, TC8
Timer/Counter 6, 7 and 8
16K Bytes
0xFFFA C000
0xFFFA FFFF
MCI
Multimedia Card Interface
16K Bytes
0xFFFB 0000
0xFFFB 3FFF 0xFFFB 4000
UDP
USB Device Port
16K Bytes
Reserved
0xFFFB 7FFF
0xFFFB 8000
0xFFFB BFFF 0xFFFB C000
TWI
Two-Wire Interface
16K Bytes
Reserved 0xFFFC 0000
0xFFFB FFFF
USART0
0xFFFC 3FFF
Universal Synchronous Asynchronous Receiver Transmitter 0 Universal Synchronous Asynchronous Receiver Transmitter 1 Universal Synchronous Asynchronous Receiver Transmitter 1 PWM Controller Serial Synchronous Controller 0
16K Bytes
0xFFFC 4000
0xFFFC 7FFF
USART1
16K Bytes
0xFFFC 8000
USART2
16K Bytes
0xFFFC BFFF
0xFFFC C000 PWMC
0xFFFC FFFF
16K Bytes
0xFFFD 0000
0xFFFD 3FFF
SSC0
16K Bytes
0xFFFD 4000
0xFFFD 7FFF
SSC1
Serial Synchronous Controller 1
16K Bytes
0xFFFD 8000
0xFFFD BFFF
ADC0
Analog-to-Digital Converter 0
16K Bytes
0xFFFD C000
0xFFFD FFFF
ADC1
Analog-to-Digital Converter 1
16K Bytes
0xFFFE 0000
0xFFFE 3FFF
SPI0
Serial Peripheral Interface 0
16K Bytes
0xFFFE 4000
0xFFFE 7FFF 0xFFFE 8000
SPI1
Serial Peripheral Interface 1
16K Bytes
Reserved
0xFFFE FFFF
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10.2 Peripheral Multiplexing on PIO Lines
The AT91SAM7A3 features two PIO controllers, PIOA and PIOB, which multiplex the I/O lines of the peripheral set. PIO Controllers A and B control respectively 32 and 30 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with Analog Input of both ADC Controllers. Table 10-1 on page 28 and Table 10-2 on page 29 define how the I/O lines of the peripherals A, B or Analog Input are multiplexed on the PIO Controllers A and B. The two columns "Function" and "Comments" have been inserted for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only may be duplicated within both tables. At reset, all I/O lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset occurs.
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10.3
PIO Controller A Multiplexing
Multiplexing on PIO Controller A
PIO Controller A Application Usage Comment Function Comments
Table 10-1.
I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
Peripheral A TWD TWCK RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 RXD2 TXD2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 CANRX0 CANTX0 CANRX1 CANTX1 DRXD DTXD
Peripheral B ADC0_ADTRG ADC1_ADTRG
SPI1_NPSC0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK
MCDA1 MCDA2 MCDA3 MCDA0 MCCDA MCCK PCK0 PCK1 PCK2 PCK3 IRQ0 IRQ1 TCLK4 TCLK5
TCLK3 TCLK6 TCLK7 TCLK8
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10.4 PIO Controller B Multiplexing
Multiplexing on PIO Controller B
PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 Peripheral A IRQ2 IRQ3 TF0 TK0 TD0 RD0 RK0 RF0 FIQ TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 TIOA6 TIOB6 TIOA7 TIOB7 TIOA8 TIOB8 RTS1 CTS1 SCK1 RTS2 CTS2 SCK2 Peripheral B PWM5 PWM6 PWM7 PCK0 PCK1 PCK2 PCK3 CANTX1 TF1 TK1 RK1 RF1 TD1 RD1 PWM0 PWM1 PWM2 PWM3 PWM4 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 ADC0_AD0 ADC0_AD1 ADC0_AD2 ADC0_AD3 ADC0_AD4 ADC0_AD5 ADC0_AD6 ADC0_AD7 ADC1_AD0 ADC1_AD1 ADC1_AD2 ADC1_AD3 ADC1_AD4 ADC1_AD5 ADC1_AD6 ADC1_AD7 Comment Application Usage Function Comments
Table 10-2.
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11. Peripheral Identifiers
The AT91SAM7A3 embeds a wide range of peripherals. Table 11-1 defines the Peripheral Identifiers of the AT91SAM7A3. Unique peripheral identifiers are defined for both the AIC and the PMC. Table 11-1.
Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Peripheral Identifiers
Peripheral Mnemonic AIC SYSC PIOA PIOB CAN0 CAN1 US0 US1 US2 MCI TWI SPI0 SPI1 SSC0 SSC1 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 ADC0 ADC1
(1) (1) (1)
Peripheral Name Advanced Interrupt Controller
External Interrupt FIQ
Parallel I/O Controller A Parallel I/O Controller B CAN Controller 0 CAN Controller 1 USART 0 USART 1 USART 2 Multimedia Card Interface Two-wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 Timer/Counter 4 Timer/Counter 5 Timer/Counter 6 Timer/Counter 7 Timer/Counter 8 Analog-to Digital Converter 0 Analog-to Digital Converter 1 PWM Controller USB Device Port Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 IRQ3
PWMC UDP AIC AIC AIC AIC
Note:
1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller and ADC are continuously clocked.
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11.1 Serial Peripheral Interface
* Supports communication with external serial devices - Four chip selects with external decoder allow communication with up to 15 peripherals - Serial memories, such as DataFlash(R) and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays per chip select between consecutive transfers and between clock and data - Programmable delay between consecutive transfers - Selectable mode fault detection - Maximum frequency at up to Master Clock
11.2
Two-wire Interface
* Master Mode only * Compatibility with standard two-wire serial memories * One, two or three bytes for slave address * Sequential read/write operations
11.3
USART
* Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection - By 8 or by 16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * IrDA modulation and demodulation - Communication at up to 115.2 Kbps * Test Modes
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6042DS-ATARM-14-Dec-06
- Remote Loopback, Local Loopback, Automatic Echo
11.4
Serial Synchronous Controller
* Provides serial synchronous communication links used in audio and telecom applications * Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
11.5
Timer Counter
* Three 16-bit Timer Counter Channels * Wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs as defined in Table 11-2. Table 11-2. Timer Counter Clock Assignment
TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
- Two multi-purpose input/output signals - Two global registers that act on all three TC Channels
11.6
PWM Controller
* Eight channels, one 20-bit counter per channel * Common clock generator, providing thirteen different clocks - A Modulo n counter providing eleven clocks - Two independent linear dividers working on modulo n counter outputs * Independent channel programming
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- Independent enable/disable commands - Independent clock selection - Independent period and duty cycle, with double buffering - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform
11.7
USB Device Port
* USB V2.0 full-speed compliant,12 Mbits per second. * Embedded USB V2.0 full-speed transceiver * Six endpoints - Endpoint 0: 8 bytes - Endpoint 1 and 2: 64 bytes ping-pong - Endpoint 3: 64 bytes - Endpoint 4 and 5: 512 bytes ping-pong * Embedded 2,376-byte dual-port RAM for endpoints - Ping-pong Mode (two memory banks) for bulk endpoints * Suspend/resume logic
11.8
Multimedia Card Interface
* Compatibility with MultiMedia card specification version 2.2 * Compatibility with SD Memory card specification version 1.0 * Cards clock rate up to Master Clock divided by 2 * Embeds power management to slow down clock rate when not used * Supports up to sixteen slots (through multiplexing) - One slot for one MultiMedia card bus (up to 30 cards) or one SD memory card * Supports stream, block and multi-block data read and write * Supports connection to Peripheral Data Controller - Minimizes processor intervention for large buffer transfers
11.9
CAN Controller
* Fully compliant with CAN 2.0B active controllers * Bit rates up to 1Mbit/s * 16 object-oriented mailboxes, each with the following properties: - CAN specification 2.0 Part A or 2.0 Part B programmable for each message - Object-configurable as receive (with overwrite or not) or transmit - Local tag and mask filters up to 29-bit identifier/channel - 32-bit access to data registers for each mailbox data object - Uses a 16-bit time stamp on receive and transmit messages - Hardware concatenation of ID unmasked bit fields to speed up family ID processing - 16-bit internal timer for Time Stamping and Network synchronization - Programmable reception buffer length up to 16 mailbox object
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6042DS-ATARM-14-Dec-06
- Priority management between transmission mailboxes - Autobaud and listening mode - Low power mode and programmable wake-up on bus activity or by the application - Data, remote, error and overload frame handling
11.10 Analog-to-Digital Converter
* 8-channel ADC * 10-bit 384K, or 8-bit 533K, samples/sec Successive Approximation Register ADC * -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity * Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs * Individual enable and disable of each channel * External voltage reference for better accuracy on low-voltage inputs * Multiple trigger sources - Hardware or software trigger - External pins: ADTRG0 and ADTRG1 - Timer Counter 0 to 5 outputs: TIOA0 to TIOA5 * Sleep Mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels * All analog inputs are shared with digital signals
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12. Package Drawing
Figure 12-1. 100-lead LQFP Package Drawing
35
6042DS-ATARM-14-Dec-06
Table 12-1.
100-lead LQFP Package Dimensions
Millimeter Inch Max 1.60 0.05 1.35 1.40 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.08 0.08 0 0 11 11 0.09 0.45 0.60 1.00 REF 0.20 0.17 0.20 0.50 BSC 12.00 12.00 Tolerances of form and position 0.27 0.008 0.007 0.008 0.020 BSC 0.472 0.472 0.011 12 12 13 13 0.20 0.75 3.5 7 0.20 0.003 0.003 0 0 11 11 0.004 0.018 0.024 0.039 REF 12 12 13 13 0.008 0.030 3.5 7 0.15 1.45 0.002 0.053 0.055 0.630 BSC 0.551 BSC 0.630 BSC 0.551 BSC 0.008 Min Nom Max 0.63 0.006 0.057
Symbol A A1 A2 D D1 E E1 R2 R1 Q 1 2 3 c L L1 S b e D2 E2
Min
Nom
aaa bbb ccc ddd
0.20 0.20 0.08 0.08
0.008 0.008 0.003 0.003
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AT91SAM7A3
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13. Ordering Information
Table 13-1. Ordering Information
Ordering Code AT91SAM7A3-AU Package LQFP100 Package Type Green Temperature Operating Range Industrial (-40C to 85C)
37
6042DS-ATARM-14-Dec-06
Revision History
Version AS Version BS Version CS 23-Dec-04 30-Sep-05 21-Nov-05
Version 6042AS 6042BS
Comments First issue
Change Request Ref.
In Features, corrected number of battery backup registers. Updated Page Programming Time. Changed information on static operation. Changed signal names VDDIN and VDDIO to VDD3V3 and VDDOUT and VDDCORE to VDD1V8. Removed signal names GNDANA, GNDBU and GNDPLL in Figure 2-1, "AT91SAM7A3 Block Diagram" , Table 3-1, "Signal Description" and Table 4-1, "Pinout in 100-lead LQFP Package" . Changed SPI and ADC signal names. Updated Section 5.1 on page 10 with new signal names and new information. Updated Figure 5-1, "3.3V System Single Power Supply Schematics" with new signal names. Updated Section 8.1 "Embedded Memories" on page 15 with correct lock region size. Updated Section 8.3 on page 17 with information on standby mode for Flash. Updated Figure 9-1, "System Controller Block Diagram" with new signal names. Corrected addresses. Corrected start and end addresses of GPBR in Figure 9-2, System Controller Mapping., . Updated chip ID reference in "Debug Unit" . Updated Table 13-1, "Ordering Information" with new ordering information. 6042CS In Features, and global "EmbeddedICETM In-circuit Emulation, Debug Communication Channel Support" Embedded ICE to replace usage of "embedded in-circuit emulation". 6042DS Section 4.1, "100-lead LQFP Package Outline" replaces Mechanical Overview, Figure 4-1, "100-lead LQFP Outline (Top View)" replaced. Figure 8-1, "AT91SAM7A3 Memory Mapping", Peripheral and System Controller Memory Maps consolidated. Figure 12., "Package Drawing", Figure 12-1 on page 35, Table 12-1 on page 36 added Table 3-1, "Signal Description," on page 5, SHDW and FWUP, comments updated Table 11-1, "Peripheral Identifiers," on page 30, SYSIRQ changed to SYSC. Figure 8-2, "Internal Memory Mapping" reference to boot memory removed.
05-232
05-440
05-234
SJO Legal
3179
rfo
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AT91SAM7A3
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